Lithographic projection apparatus (tools) can be used, for example, in the manufacture of integrated circuits (ICs). When using the various tools, a mask can be used that contains a circuit pattern corresponding to an individual layer of the IC, and this pattern, usually having many designs, can be imaged onto a target portion (e.g., comprising one or more dies) on a substrate, such as a silicon or other wafer comprising a semiconductor, that has been coated with a layer of radiation-sensitive material, such as a resist. In general, a single wafer may contain a network of adjacent target portions that can be successively irradiated using a projection system of the tool, one at a time.
One of the goals in IC fabrication is to faithfully reproduce the original circuit design on the wafer using the mask. Another goal is to use as much of the wafer real estate as possible. As the size of an IC is reduced and its density increases, however, the critical dimension (CD) of its corresponding mask approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool can be defined as the minimum feature sizes that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure tools often constrains the CD for many advanced IC designs.
To achieve these goals, techniques utilizing resolution-enhanced optical lithography technology (“RET”) have become popular as techniques for providing patterns with sub-wavelength resolution. These methods include alternating phase-shifting mask (“altPSM”) lithography, attenuated phase-shifting mask (“attPSM”) lithography, and binary lithography. In altPSM, for example, opposite phases of light are shed on two sides of a critical feature such that the destructive interference between the opposite light phases can make the printed shape sharper. Generally, the critical features are imaged using a phase shift photomask and the non-critical and trim features are imaged in a second exposure using a conventional chrome-on-glass mask, such as a structure or trim photomask. In this process, a mask, or “reticle”, includes a semiconductor circuit layout pattern typically formed of opaque chrome, on a transparent glass (typically SiO2) substrate. A stepper includes a light source and optics/lenses that project light coming through the reticle and images the circuit pattern, typically with a 4× to 5× reduction factor, on a photo-resist film formed on a silicon wafer. The term “chrome” refers to an opaque masking material that is typically but not always comprised of chrome.
Further, transistor matching requirements for advanced technology nodes, such as less than 1.0 μm, require exquisite CD control, beyond the capability of current lithography and etch tools and processes. An important component of variation is matching between gates in the interior of an array of active gates, e.g., over the same active region, and those on the end of the array. For example, for the 45 nm technology node, the CD variation for the end gates in an array of gates can be a factor of 2 to 3 times larger than that of the interior active gates of the array.
For example, FIG. 1A shows a conventional gate array 100 having end gates 110a and 110b and interior gates 120a, 120b, and 120c formed on substrate 130. Conventional gate array 100 is formed using a conventional lithography process, such as altPSM, attPSM, or binary lithography. One problem is that end gates 110a and 110b can have two to three times more variation in size than internal gates 120a, 120b, and 120c. As shown in FIG. 1A, the conventional processes can form end gates that can vary in size from, for example, 110a and 110b that are similar in size to interior gates 120a-c to 110a′ and 110b′ that are 2 to 3 times larger than interior gates 120a-c. This size variation can affect transistor leakage and performance.
In some instances, dummy gates, such as dummy gates 110a and 110b shown in FIG. 1B, are formed on a substrate 130 adjacent to interior gates 120a and 120c, respectively, to aid the control and sizing of internal gates 120a-c. Problems arise in conventional processes because dummy gates remain on the wafer even after the device is complete. Dummy gates residing on the wafer are then processed in a similar way as active gates are processed. For example, sidewall spacers 112 are subsequently formed on the sides of the dummy gates 110a and 110b. Problems occur because the sidewall spacers on the dummy gates can increase or decrease stress (e.g., compressive and/or tensile) on the active interior gates thereby interfering with device performance. Further, the presence of the dummy gates can cause unwanted polysilicon capacitance. In addition, the dummy gates can be a source of defect problems, for example breaking over the gate oxide, during further processing. In an attempt to compensate for this interference, dummy gates must be formed far away from the active gates, as shown in FIG. 1B. As such, dummy gates are spaced at pitches significantly different than the pitch of active gates taking up valuable real estate on the chip.
Thus, there is a need to overcome these and other problems of the prior art to control the size of features formed on a substrate.